Title:  Machine Learning in Physical Design for 2D and 3D Integrated Circuits

Committee:

Dr. Sung Kyu Lim, ECE, Chair, Advisor

Dr. Shimeng Yu, ECE

Dr. Saibal Mukhopadhyay, ECE

Dr. Siddhartha Nath, Intel

Dr. Celine Lin, CoC

Abstract: The objective of this research is to develop ML algorithms that improve the final outcomes and productivity of PD implementations for 2D and 3D integrated circuits (ICs). In particular, various supervised, unsupervised, and reinforcement learning (RL) algorithms are devised to tackle a broad spectrum of traditional PD problems, which are categorized into four major themes in this dissertation. In the first theme, unsupervised learning algorithms are developed to perform tier partitioning in monolithic 3D (M3D) ICs, and clustering-based placement optimization. In the second theme, generative adversarial learning algorithms are devised to improve global placement of open-source placers, and optimize CTS outcomes of commercial tools. In the third theme, RL frameworks are constructed to perform gate sizing for timing optimization, and drive concurrent clock and data (CCD) optimization via intelligent endpoint prioritization. In the fourth theme, supervised learning models are presented to predict threshold voltage assignment for leakage power optimization, and full-flow doomed run prediction.